1. Field of the Invention
The invention relates to a method of producing a multilayer circuit board in which a plurality of wiring layers (routing layers) are formed on a core substrate by a build-up process.
2. Description of the Related Art
A multilayer circuit board typically comprises a core substrate and a plurality of wiring layers built up on both sides of the core substrate, with an insulation layer being interposed therebetween. FIG. 6 illustrates such a multilayer circuit board 8 comprising a core substrate 10, wiring layers each comprising patterned wiring lines (routing lines) 12a, 12b provided on both sides of the core substrate 10, and insulation layers 14a, 14b. The wiring lines 12a and 12b on each of the sides of the core substrate 10 are electrically connected with each other by a via 16a provided in the insulation layer 14a, the via usually having a diameter of about 80 micrometers and a depth of about 40 to 50 micrometers. The wiring lines 12a, 12b on one side of the core substrate 10 are connected with the wiring lines 12a, 12b on the other side of the core substrate 10 by a conducting member 20 formed on the inside wall of a through hole 18 which pierces through the core substrate 10, the through hole usually having a diameter of about 200 to 300 micrometers. The inside of the conducting member 20 on the inside wall of the through hole 18 is filled with an insulation material 22 such as a resin.
A build-up process for the manufacture of the multilayer circuit board 8 depicted in FIG. 6 is illustrated in FIGS. 7A to 7C. In the process of FIGS. 7A to 7C, first patterned wiring lines 12a are formed on both sides of the core substrate 10, as shown in FIG. 7A which illustrates only one side of the substrate 10 for simplicity. The wiring lines 12a are then covered with an electrical insulation layer 14a, and through holes 18 are formed to pierce through the insulation layers 14a on both sides of the core substrate 10 and the core substrate 10 itself. Subsequently, as illustrated in FIG. 7B, via holes 15a are formed in the insulation layer 14a for subsequent formation of vias. The substrate 10 provided with the insulation layer having via holes 15a is then subjected to electroless plating and electroplating, to thereby form a continuous conductor layer 30 to cover the insides of the via hole 15a and the through hole 18, and the insulation layer 14a, as illustrated in FIG. 7C. Portions of the continuous conductor layer 30 in the insides of the through holes 18 are subsequently formed into the conducting member 20 (FIG. 6), and portions of the continuous conductor layer 30 on the top surface of the insulation layer 14a and in the inside of the via holes 15a are formed into the second patterned wiring lines 12b (FIG. 6) and the vias 16a (FIG. 6), respectively, by etching the continuous conductor layer 30.
In the manufacture of a multilayer circuit board using a build-up process as described above, the continuous conductor layer 30 is formed simultaneously on the insides of the through holes 18 and the via holes 15a by plating. In such a case, where plating is carried out under circumstances where through holes 18 and via holes 15a coexist, a plated layer in the inside of the through hole 18 has a smaller thickness relative to a thickness of a plated layer in the inside of the via hole 15a, in general. This is because the deposition of plating material from a plating bath to a surface to be plated varies between the through hole 18 having no bottom and the via hole 15a having a bottom, depending on plating conditions such as the composition of the plating bath used.
In a typical multilayer circuit board produced by a conventional build-up process, the via 16a (FIG. 6), which is made up of the portion of conductor layer deposited on the inside wall and the bottom of the via hole 15a in FIG. 7C, electrically connects wiring lines 12a and 12b of the adjacent layers with each other, and the via hole 15a is not filled with the plated conductor material. For a multilayer circuit board of a high mounting density, it is useful that it has vias filled with a conductor material, which are called xe2x80x9cfilled viasxe2x80x9d and can be arranged with a high density.
To fill the via holes 15a by plating, a plating solution which contains an additive that does not accelerate a rate of plating on the insulation layer 14a to thereby form thereon a conductor layer of a smaller thickness but accelerates a rate of plating in the via holes 15a, is used. When a plating solution contains such a suitable additive for the formation of filled vias, however, the conductor layer formed on the inside wall of the through hole 18 also has a smaller thickness like the conductor layer formed on the insulation layer 14a. 
An object of the invention is to provide a method of producing a multilayer circuit board having a plurality of layers of wiring lines on both sides of a core substrate, which makes it possible to fill via holes with a conductor material to provide filled vias capable of being arranged in a high density, and also form a reliable conducting member in the through holes, by plating under circumstances that the via holes and the through holes coexist.
According to the invention, a multilayer circuit board which comprises a core substrate and a plurality of layers of wiring lines on both sides of the core substrate, the layers of wiring lines being on each side of the substrate with an insulation layer being interposed therebetween, the layers of wiring lines on both sides being interconnected by conducting members provided on the inside walls of through holes going through the core substrate, and the layers of wiring lines on each side of the core substrate being connected with each other by vias of a conductor material going through the interposed insulation layer, is produced by a method comprising, on each of sides of the core substrate, alternately forming a layer of wiring lines and an insulation layer while connecting a lower layer of wiring lines with an upper layer of wiring lines by vias, wherein the conducting member on the inside wall of the through hole and the via are formed in separate steps.
In an embodiment of the invention, the method comprises the following steps: providing a core substrate having a patterned first layer of wiring lines formed on each side thereof, forming an insulation layer on each side of the core substrate to cover the entire area of the substrate provided with the first layer of wiring lines, forming through holes extending from one side to the other side of the core substrate piercing through the insulation layer on both sides of the core substrate and the core substrate itself, forming via holes in the insulation layer on each side of the core substrate to expose parts of the layer of wiring lines at the bottom, forming a continuous conductor layer to cover the inside walls of the through holes, the insulation layer, and the exposed parts of the layer of wiring lines, filling the through holes with an insulation material such as a resin, filling the via holes with a conductor material, forming a conductor layer on the continuous conductor layer covering the insulation layer to provide a lamination of two conductor layers, simultaneously with or separately from the step of filling the via holes, and patterning the lamination of two conductor layers to thereby provide a second layer of wiring lines.
In another embodiment of the invention, the method comprises the following steps: providing a core substrate, forming through holes in the core substrate, forming a continuous conductor layer on each side of the substrate and the inside walls of the through holes, filling the through holes with an insulation material such as a resin, patterning the continuous conductor layer to form a first layer of wiring lines, forming an insulation layer on each side of the core substrate to cover the entire area of the substrate provided with the first layer of wiring lines, forming via holes in the insulation layer on each side of the core substrate to expose parts of the first layer of wiring lines at the bottom, filling the via holes with a conductor material, forming a conductor layer on the insulation layer, simultaneously with or separately from the step of filling the via holes, and patterning the conductor layer to thereby provide a second layer of wiring lines.
In this embodiment, the first layer of wiring lines may be formed by forming an additional conductor layer on the continuous conductor layer to provide a lamination of two conductor layers on the insulation layer, and then patterning the lamination of two conductor layers.
In a further embodiment of the invention, the method comprises the following steps: providing a core substrate having a patterned first layer of wiring lines formed on each side thereof, forming an insulation layer on each side of the core substrate to cover the entire area of the substrate provided with the first layer of wiring lines, forming through holes extending from one side to the other side of the core substrate piercing through the insulation layer on both sides of the core substrate and the core substrate itself, forming a continuous conductor layer to cover the inside walls of the through holes and the insulation layer, filling the through holes with an insulation material such as a resin, patterning the continuous conductor layer to provide a second layer of wiring lines, forming an additional insulation layer to cover the formerly formed insulation layer provided thereon with the second layer of wiring lines, forming via holes piercing through the two insulation layers to expose parts of the first layer of wiring lines at the bottom, filling the via holes with a conductor material, forming a conductor layer on the top of the two insulation layers, simultaneously with or separately from the step of filling the via holes, and patterning the conductor layer to thereby provide a second layer of wiring lines.
In this embodiment, the second layer of wiring lines may be formed by forming an additional conductor layer to cover the continuous conductor layer and the ends of the insulation material filled in the through holes to provide a lamination of two conductor layers, and then patterning the lamination of two conductor layers.